1. Field of the Invention
The present invention relates to an improved display control system for a computer.
2. Description of the Prior Art
FIG. 1 illustrates a block diagram of a conventional color graphics display system.
In this figure, there is provided a CPU(microprocessor) 1 for controlling the whole system, to which a main memory 2 and a display control circuit 3 are connected. The main memory 2 is used to hold programs and data, while the display control circuit 3 is dedicated to controlling color graphics display. In FIG. 1, reference numeral 4 designates a VRAM (video memory) to hold data for CRT display, and numeral 5 represents a CRT color display unit.
FIG. 2 illustrates a block diagram of an example of the display control circuit 3 shown in FIG. 1.
A clock signal generated by a timing controller 11 is input to a counter 12 which comprises a column counter, a line counter and a row counter. The counter 12 generates a CRT display synchronous signal via a display timing circuit 13, while it also creates a display address and outputs it as a VRAM address via a multiplexer 15.
The read data for display access from the VRAM 4 is inputted via a buffer 19 to a video output controller 20 to create a CRT video signal.
On the other hand, when CPU 1 accesses VRAM 4, the address of VRAM 4 is set in a VRAM address register 14. Then, if a write strobe is input to a CPU interface controller 18, then Multiplexer 15 selects the output of the VRAM address register 14 to be accessed by CPU 1 as a VRAM address, and the write data from CPU 1 is written into VRAM 4 via the buffers 16, 17.
FIG. 3 illustrates an example of the above-mentioned VRAM 4. The illustrated VRAM 4 has a series of physical addresses as a memory unit, and, logically, it has a such a display screen structure as shown which comprises 640 horizontal dots, 200 vertical dots and 4-bit color information (16 colors).
Now let us consider an operational example: that is, an operation in which on the display screen shown in FIG. 3 the block data of the source area in VRAM 4 is transferred to a destination area based on the X, Y coordinates.
CPU 1 calculates the physical address of VRAM 4 based on the coordinates (Sx, Sy) of the source area and sets it in the VRAM address register 14 within the display control circuit 3. CPU 1 also outputs a read command and reads out the color data in VRAM 4 which corresponds to the coordinates (Sx, Sy).
Next, CPU 1 calculates a physical address in VRAM 4 based on the coordinates (Dx, Dy) of a destination area to which the block data is to be transferred, and sets it in the VRAM address register 14 within the display control circuit 3. CPU 1 also outputs the color data and write command and writes them into VRAM 4 corresponding to the coordinates (Dx, Dy).
Thus, the above-mentioned read/write procedure must be repeated NX times regarding a horizontal direction and NY times regarding a vertical direction, that is, (NX.times.NY) times to be able to transfer the block data of the source area to the destination area.
As can be understood from the foregoing description, the conventional display control system for a personal computer is designed to have reduced amounts of hardware on its internal structure and interfaces such as gates and IC elements so as to satisfy the needs for a compact computer and for reduced costs. This increases the load of software accordingly.
A figure forming processing includes a line command which provides the start coordinates (DXo, DYo) of a straight line to be formed, as well as the amounts of displacement in both the X-coordinate direction (horizontal direction) and Y-coordinate direction (vertical direction) of the straight line so as to form the straight line. To execute the line command, not only the calculation of the coordinates of the line but also a logical operation between the line coordinates and the color code data on the picture being now displayed are necessary.
FIG. 3A is a view to explain the execution of the above-mentioned line command. We will now consider an example of operation of a line command to form a line from the start coordinates (DXo, DYo), on the display screen shown in FIG. 3A.
First, CPU 1 calculates the physical address of VRAM 4 from the start coordinates (DXo, DYo) and sets the calculated physical address in the VRAM address register 14 within the display control circuit 3. Also, CPU 1 outputs a read command and reads out the color code data within VRAM 4 corresponding to the start coordinates (DXo, DYo). Further, CPU 1 performs a logical operation between the read-out color code data and a predetermined type of data to create new color code data on a straight line.
The color code data on a line created is written by a write command into the locations of VRAM 4 correspond-ing to the start coordinates (DXo, DYo).
Next, CPU 1 carries out a coordinate calculation to obtain the coordinates (DX1, DY1) of the second dot forming a line to be formed. Then, in a similar operation, the color code data on the line is written into VRAM 4. Next, the coordinates (DX2, DY2) of the third dot are calculated and the associated color code data is written into VRAM 4. In this manner, the above-mentioned operation can be sequentially repeated NX times to form the line on the screen.
As can be seen from the example of the above-mentioned block data transfer, in the conventional display control system, all of the processings must be performed by CPU 1 and thus it takes a lot of time to transfer the block data.
On the other hand, normally, CPU 1 and the display control circuit 3 are operated independently of each other and the display timing of the display control circuit 3 is given a higher priority than the VRAM access timing of CPU 1. Thus, a wait time occurs in access to VRAM 4 from CPU 1, which decrease the performance of the data transfer extremely.
Accordingly, in the above-mentioned prior art display control system, since its software must play a greater role in display control, there is a problem that it takes a very long time to execute its display control operation. Also, when a computer is up-graded with increased display specifications and a plurality of display modes, the address calculation is further complicated and thus the time necessary for execution of its operation is outstandingly extended.
In addition, in the prior art display control system, since, as can be understood from the above-mentioned example of operation of the conventional line command, all of the processings must be performed by CPU 1 and thus extremely much time is required for the read/write of the color code data, coordinates calculation and physical address calculation, there exists a problem that the processing performance of the line command is low.